1. Field of the Invention
The present invention relates to bias circuits for generating bias voltages and currents. More specifically, the present invention relates to the generation of low voltages using a low supply voltage.
2. Description of Related Art
Many systems that manipulate and generate analog and digital signals need precise, stable voltage and current references defining bias points for these signals. In many cases, these voltage references must be in addition to and independent of a supply voltage for the circuit. In Dynamic Random Access Memories (DRAM), as well as other semiconductor devices, some of these applications are in areas such as, sense amplifiers, input signal level sensors, phase locked loops, delay locked loops, and various other analog circuits.
Various techniques exist for generating these supply voltages. Traditional bias generation techniques vary from a simple resistor voltage divider to complex bandgap reference circuits. These reference voltages may typically need to be independent from a source supply voltage. Unfortunately, as supply voltages become lower in modern low power and deep submicron designs, bias generating techniques become more difficult. Many traditional techniques require a supply voltage significantly higher than the desired reference voltage and do not scale proportionally as the supply voltage decreases.
A voltage reference may be created from a traditional and simple voltage divider circuit using resistors in series or diode-connected metal-oxide semiconductor (MOS) transistors in series. Unfortunately, the resultant reference voltage is a function of the supply voltage and controlling the resistance precision of the resistors or transistors may be difficult. Voltage dividers are, therefore, not an adequate solution when supply independence is required.
Bandgap reference sources are quite flexible and may generate supply independent reference voltages, sometimes even with a relatively low supply voltage. However, bandgap reference circuits tend to be complex requiring complicated analog amplifier feedback, significant area on a semiconductor die, and relatively high operating currents. As a result, bandgap references have significant disadvantages in low power applications.
Complementary MOS (CMOS) circuits are often used to generate supply independent reference voltages using transistor threshold voltages (Vt) to generate a reference. These circuits typically have the advantage of being small in area, relatively simple, and relatively independent from the supply voltage. However, Vt referenced bias sources typically require a relatively high supply voltage to generate the reference voltage. FIG. 1 illustrates a conventional Vt referenced bias circuit.
The FIG. 1 circuit, as well as the present invention, contains two well-known circuit configurations known as diode-connected transistors and current mirrors.
A diode-connected transistor is formed when the gate and drain of the transistor are connected together. For example, in the bias circuit shown in FIG. 1, the p-channel transistor P11 is connected in a diode configuration. The P21 transistor operates in the saturation region because the gate and drain are connected to the same potential. As a result, the transistor operates with voltage to current properties similar to a p-n junction diode.
A current mirror is a configuration comprising two transistors of the same type (e.g., both p-channels or both n-channels) in which the sources of the transistors are connected together and the gates of the transistors are connected together. Current mirrors operate on the theory that if the two transistors are similarly processed and have sizes W/L (i.e., width/length) in a defined proportion N, then the current relationship through the two transistors will have the same proportion N. For example, in bias circuit shown in FIG. 1, if the reference transistor P11 and the first current mirror P12 have the same W/L, they will have substantially the same amount of current flowing through them. This is so because both transistors are connected to the same source, and have the same gate-to-source voltage, which defines the magnitude of the drain current. Typically, current mirrors are designed with the two transistors having the same size (i.e., the proportion N=1). However, other proportions may be used.
Referring to the bias circuit 10 in FIG. 1, the current mirror configuration of p-channel transistor P11 and first current mirror P12 causes the currents I11 and 12 through P11 and P12, respectively, to be proportional to each other. In most applications, P11 and P12 are the same size resulting in substantially the same currents for I11 and 112. The I11 current flowing through p-channel P11 also flows through n-channel transistor N11. For current to flow through N11, the gate-to-source voltage on N11 must be at or above a threshold voltage. This gate voltage is supplied by the voltage drop across resistor R12. However, the n-channel transistor N12 in series with R12 regulates the amount of current flowing through R12. For current to flow in N12, the gate-to-source voltage of N12 must also be at or above a threshold voltage. However, the source of N12 is already at least a threshold voltage above ground due to the voltage drop through R12. Therefore, the gate voltage of N12 must be at least two threshold voltages above ground for N12 to conduct. This stacked configuration of R12, N11, and N12, creates a feedback loop wherein increased current through N12 raises the gate voltage on N11, increasing the current through N11. However, increased current through N11 reduces the gate voltage on N12, thereby reducing the current through N12. The feedback loop reaches an equilibrium defining the amount of current flowing through N11 and, as a result, P11. This feedback configuration is often termed a “cascade” arrangement due to the stacked nature of the n-channel transistors. Unfortunately, the cascade arrangement increases the required supply voltage.
The lowest possible supply voltage is equal to the sum of the threshold voltages of N11, N12, and P11. In the FIG. 1 bias ciruit 10, a third p-channel transistor P13 is typically configured as another current mirror to generate a stable buffered current I13 through P13, which is proportional to the current through P11.
Because the FIG. 1 bias circuit generates a reference voltage across multiple stacked gate-to-source voltage drops, it requires the supply voltage to be higher than the gate-to-gate source voltage of the stacked transistors. As a result, the circuit in FIG. 1 is not suitable for low supply voltage applications.
There is a need for a simple Vt threshold referenced bias circuit for generating low reference voltages in a system using a low supply voltage.